1. Field of the Invention
The present invention relates to a semiconductor device including analog circuits and digital circuits, a method of controlling such a semiconductor device, and a system incorporating such a semiconductor device.
2. Description of the Related Art
Semiconductor devices include various circuits which are generally categorized into digital circuits and analog circuits. A digital circuit is a circuit for handling logic signals that can be represented by logic values according to binary logic or the like, e.g., performing various logic operations on logic signals and inputting and outputting logic signals. The digital circuit is also known as a logic circuit. A delay circuit for giving a time delay to a logic signal can be constructed as a digital circuit. An analog circuit, which refers to all circuits other than digital circuits, is a circuit for handling signals that cannot be represented by logic values and continuously variable signals indicative of physical quantities. Typical analog circuits include an amplifying circuit such as sense amplifier.
Many semiconductor devices are of a hybrid nature including both digital circuit portions and analog circuit portions. For example, one such semiconductor device is a dynamic random access memory (DRAM). The DRAM has a memory array area including sense amplifiers as analog circuits and a control circuit as a digital or logic circuit for controlling the operation timing of a memory array, i.e., the timing to activate the sense amplifiers.
The operational speeds of the circuits of a semiconductor device depend on the power supply voltages that are supplied to those circuits. Generally, a circuit which is supplied with a higher power supply voltage has a higher operational speed, and a circuit which is supplied with a lower power supply voltage has a lower operational speed. Digital or logic circuits may have their operational speeds less dependent on their power supply voltages, and analog circuits may have their operational speeds more dependent on their power supply voltages. If one semiconductor device has a plurality of logic circuit blocks, then these logic circuit blocks have their operational speeds equally tending to be dependent on their power supply voltages. Even when the power supply voltages of the logic circuit blocks change, the operational speeds of the logic circuit blocks do not greatly change relatively to each other. However, if one semiconductor device has logic circuit blocks and analog circuit blocks, then when their power supply voltages change, the operational speeds of the logic circuit blocks and the analog circuit blocks greatly change relatively to each other. In case the logic or digital circuit blocks control the analog circuit blocks, there is possibility that guarantee of normal operation of the semiconductor device will be lost.
In the memory array area of the DRAM referred to above, the operational speed of the control circuit which controls the timing to activate the memory array is less dependent on its power supply voltage, whereas the operational speeds of the sense amplifiers to amplify data stored in memory cells are more dependent on their power supply voltages. For guaranteeing normal operation of the memory array area, it is necessary to eliminate a mismatch between the operational speeds of the control circuit and the memory array. Since it is difficult to make the operational speeds of the sense amplifiers less dependent on their power supply voltages, efforts need to be made to eliminate the operational speed mismatch by making the timing of signals supplied from the control circuit to the sense amplifiers, as dependent on power supply voltages as the operational speeds of the sense amplifiers are dependent on their power supply voltages.
As a technology for compensating for a change in the operational speed of an analog circuit caused by an external factor, there is disclosed a semiconductor integrated circuit which can changes delay time of a delayed clock signal in synchronism with a change in frequency of an input clock signal, in US 2001/0048331 A1. The disclosed semiconductor integrated circuit employs a delay circuit comprising a plurality of CMOS (complementary metal-oxide-semiconductor) inverters connected in series for delaying a clock signal as a logic signal. The CMOS inverters of the delay circuit include respective transistors having respective sources connected to current sources which are controlled by a detection signal related to the frequency of the input clock signal. The delay circuit disclosed in US 2001/0048331 A1 has its delay time changing in synchronism with a change in the frequency of the input clock signal. US 2001/0048331 A1 is neither concerned with the elimination of a mismatch between the operational speeds of a digital circuit and an analog circuit because the operational speeds depend on their power supply voltages differently, nor suggests problems caused by the mismatch.
In a semiconductor device having an analog circuit and a digital circuit, a mismatch tends to occur between the operational speed of the analog circuit and the operational speed of the digital circuit due to a change in a power supply voltage that is supplied to the semiconductor device. If the power supply voltage changes and, for example, the operation timing of the analog circuit is controlled by an output signal from the digital circuit, then the semiconductor device is liable to fail to operate normally on account of the mismatch.